1. Field of the Invention
The present invention relates to a signal processing device, particularly to a device for clamping a video signal.
2. Description of the Related Art
In a known analog video signal input unit of a television receiver, a video tape recorder, or a digital video camera, a signal potential between a capacitor provided in series with an input signal and an input terminal of an A/D converter (ADC) is increased/decreased by a circuit including a resistor and a current source or a circuit including current sources. Also, by using a video amplifier for level shifting provided in a signal path, a pedestal level of the signal is clamped (e.g., see Japanese Patent Laid-Open No. 7-135579).
FIG. 5 shows an example of a clamp circuit in a known digital video signal processing system. As shown in FIG. 5, in the digital video signal processing system, an input analog video signal is converted to a digital signal by an A/D converter (ADC) 204 and then a pedestal level of the input video signal is detected. Then, by performing feedback control on a current source or the like so that a difference between the detected pedestal level and a desired value becomes 0 (zero), clamping control is performed.
In FIG. 5, an input signal 201 is an analog video signal. This signal is a composite signal compatible with a television signal system, such as an NTSC (National Television System Committee) system or a PAL (phase-alternation line) system. A terminating resistor 202 has impedance matching with a transmission line for transmitting the input signal 201. Herein, a terminating resistor of 75 ohms is used in accordance with a transmission line of 75 ohms, which is typical in consumer-oriented video equipment.
A coupling capacitor 203 removes a DC component and realizes AC coupling between a connected external device (not shown) and an input terminal of the ADC 204 of this circuit. The ADC 204 converts the input signal 201 to a digital signal. A digital filter 205 is a low-pass filter or a notch filter, which removes a subcarrier signal component from the input signal 201 as a composite signal and which separates a luminance signal component with SYNC (synchronization).
A synchronization signal (SYNC) detector/separator 206 separates a composite SYNC signal component from the luminance signal component with SYNC obtained from the digital filter 205. A pedestal level detector 207 detects a digital level (signal level) of a pedestal portion with reference to the composite SYNC signal component obtained from the SYNC detector/separator 206.
An error detection feedback controller 208 compares an arbitrarily-set desired value of a pedestal level with a digital value obtained by AD-converting the signal level of the input signal 201 detected by the pedestal level detector 207, so as to obtain a difference (error) therebetween. In accordance with the difference, the error detection feedback controller 208 outputs a control signal to a first current source 210 and a second current source 211 to correct the error, so as to perform feedback control.
A clamp timing controller 209 controls output timing of the control signal from the error detection feedback controller 208 based on the composite SYNC signal component obtained from the SYNC detector/separator 206. For example, by performing clamping control only in a back porch portion of a video signal, an influence on the video signal can be avoided.
The first current source 210 is disposed between a connecting line for connecting the capacitor 203 and the ADC 204 and a power supply voltage. This current source 210 is turned ON when an output value of the error detection feedback controller 208 is 1, and charges the capacitor 203 to raise the pedestal level. The second current source 211 is disposed between the connecting line for connecting the capacitor 203 and the ADC 204 and a ground. This current source 211 is turned ON when the output value of the error detection feedback controller 208 is 0, and discharges the capacitor 203 to decrease the pedestal level.
The first current source 210 may be replaced by a resistor and control may be performed by only the second current source 211. Likewise, the second current source 211 may be replaced by a resistor and control may be performed by only the first current source 210.
The input signal 201 is clamped by the first current source 210 or the second current source 211, is converted to a digital signal by the ADC 204, and is filtered through the digital filter 205. Accordingly, a digital video signal 212 is obtained. In FIG. 5, the ADC 204, the digital filter 205, the SYNC detector/separator 206, the pedestal level detector 207, the error detection feedback controller 208, and the clamp timing controller 209 are integrated to form an integrated circuit 2A.
Instead of using the first and second current sources 210 and 211, a video amplifier may be provided in a signal path after the capacitor 203 in order to shift a signal level. When a video amplifier is used, clamping control is realized by inputting an input analog signal to a positive input side of the video amplifier and inputting a control signal from the error detection feedback controller 208 to a negative input side thereof.
However, a clamp circuit of a simpler configuration capable of clamping a pedestal level of an analog video signal without using a current source or a video amplifier has been required.